中圖分類號： TN409 文獻標識碼： A DOI：10.16157/j.issn.0258-7998.209805 中文引用格式： 范君健，晁張虎，楊慶娜，等. 基于Cadence CHI和IVD VIP的多核SoC系統數據一致性驗證[J].電子技術應用，2020，46(8)：72-76. 英文引用格式： Fan Junjian，Chao Zhanghu，Yang Qingna，et al. Multi-core SoC based on Cadence CHI and IVD VIP system data coherence verification[J]. Application of Electronic Technique，2020，46(8)：72-76.
Multi-core SoC based on Cadence CHI and IVD VIP system data coherence verification
Fan Junjian1，Chao Zhanghu1，Yang Qingna1，Liu Qi1，Zhu Hong1，Shan Jianqi2
Abstract： In a multi-core SoC system, different processor cores perform a large amount of data read and write operations on memory space and device space. Maintaining cache coherence is facing severe challenges. The verification environment focused on the control flow has been very complicated, and the verification including data correctness check is more difficult due to the complicated control process and large amount of data. In response to this problem, this paper is based on Cadence CHI VIP, AXI VIP and IVD VIP to achieve system-level data coherence verification in a multi-core environment. In this paper, CHI VIP is used to issue a memory access request through the CHI protocol conversion bridge developed by the author, and AXI VIP is used to collect data that arrives in the main memory, real-time analysis and comparison of the request data of the CHI port and the access data of the AXI port by the IVD VIP，to realize stimulus generation and response inspection at a higher level of abstraction. The verification platform can perform data consistency verification at the subsystem level and system level, and has the advantages of rapid verification environment construction and complete coverage of function points.
Key words : cache coherence；subsystem verification；VIP；modular verification